In digital electronics data can either be synchronous or asynchronous. Synchronous data is basically clocked by a clock with a specific period. However, asynchronous data is not transmitted or received at a regular period. Therefore, the duration between receipt of different quantums of asynchronous data is varying.
One method of receiving data is to receive a clock signal and to clock the incoming data at every clock signal. This type of receipt of data is a synchronous type receipt. A somewhat different method must be used to receive asynchronous data. Referring to FIG. 1, in one method of data recovery, data is received by clock recovery circuitry 104. Clock recovery circuitry 104 provides a clock signal to retimer 102 so as to allow retimer 102, which is preferably a flip-flop or a DMUX, to receive the data. Therefore, clock recovery circuitry 104 recovers a clocking signal from the retrieved data and uses this to actually clock the received data.
Referring to FIG. 1a, typically, clock recovery circuitry 104 is implemented by use of a phase-lock-loop (PLL). This typically consists of phase detector 106, filter 108 and oscillator 110. While, this type of configuration is typically used, there are problems associated with such a configuration. First, good oscillators are be hard to fabricate, and, therefore, expensive. Second, an oscillator of lesser quality will not be able provide a periodic signal that is sufficient to meet that tight timing constraints of present and future high-speed electronics. Third, even high-quality oscillators may not work properly where the ambient conditions are less than ideal. Therefore, a means for receiving data without the use of an oscillator is critical.
It is an object of the present invention to provide circuitry which can be utilized to recover data without the use of an oscillator.